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HB52RD328DC-F
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Description
Note:
256 MB Unbuffered SDRAM S.O.DIMM 32-Mword x 64-bit, 100 MHz Memory Bus, 2-Bank Module (32 pcs of 16 M x 4 components) PC100 SDRAM
E0111H10 (1st edition) (Previous ADE-203-1044B (Z)) Feb. 28, 2001
The HB52RD328DC is a 16M x 64 x 2 banks Synchronous Dynamic RAM Small Outline Dual In-line Memory Module (S.O.DIMM), mounted 32 pieces of 64-Mbit SDRAM (HM5264405FTB) sealed in TCP package and 1 piece of serial EEPROM (2-kbit EEPROM) for Presence Detect (PD). An outline of the product is 144-pin Zig Za g Dua l tabs socke t type compa ct and thin pac kage . The ref ore, it make s high density mounting possible without surf ace mount tec hnology. It provide s common data inputs and outputs. De coupling ca pac itor s ar e mounted beside TCP on the module board. Do not push the cove r or drop the modules in orde r to prote ct fr om mec hanica l def ec ts, which would be electrical defects.
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Features
* Fully compatible with : JEDEC standard outline 8-byte S.O.DIMM * 144-pin Zig Zag Dual tabs socket type (dual lead out) Outline: 67.60 mm (Length) x 31.75 mm (Height) x 3.80 mm (Thickness) Lead pitch: 0.80 mm * 3.3 V power supply * Clock frequency: 100 MHz (max) * LVTTL interface * Data bus width: x 64 Non parity * Single pulsed RAS * 4 Banks can operates simultaneously and independently * Burst read/write operation and burst read/single write operation capability * Programmable burst length : 1/2/4/8/full page
This Product became EOL in October, 2005.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HB52RD328DC-F
* 2 variations of burst sequence Sequential (BL = 1/2/4/8/full page) interleave (BL = 1/2/4/8) * Programmable CE latency : 2/3 (HB52RD328DC-A6F/A6FL) : 3 (HB52RD328DC-B6F/B6FL) * Byte control by DQMB * Refresh cycles: 4096 refresh cycles/64 ms * 2 variations of refresh Auto refresh Self refresh * Low self refresh current: HB52RD328DC-A6FL/B6FL (L-version) * Full page burst length capability Sequential burst Burst stop capability
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Ordering Information
Type No. HB52RD328DC-A6F HB52RD328DC-B6F HB52RD328DC-A6FL HB52RD328DC-B6FL 2
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Frequency 100 100 100 100 MHz MHz MHz MHz
Data Sheet E0111H10
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CE latency Package 2/3 3 2/3 3
Contact pad Gold
Small outline DIMM (144-pin)
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HB52RD328DC-F
Pin Arrangement
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1pin 2pin Front side Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 Signal name Pin No. VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 VSS DQMB0 DQMB1 VCC A0 A1 A2 VSS DQ8 DQ9 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 NC VSS NC NC VCC VSS VCC A6 A8 VSS A9
Front Side
59pin 60pin
61pin 62pin
143pin 144pin
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DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 A10 (AP)
Back Side
Back side Signal name Pin No. 2 Signal name Pin No. VSS 74 76 78 80 82 84 Signal name CK1 VSS NC NC VCC DQ48
Data Sheet E0111H10 3
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4 DQ32 6 8 DQ33 DQ34 10 DQ35 12 VCC 14 16 18 DQ36 DQ37 DQ38 20 22 24 26 DQ39 VSS 28 VCC A3 30 32 34 A4 A5 36 38 VSS DQ40 40 DQ41
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86 88 90 DQ49 DQ50 DQ51 VSS 92 94 DQ52 DQMB4 DQMB5 96 98 DQ53 DQ54 100 DQ55 102 VCC 104 106 A7 A13 (BA0) VSS 108 110 A12 (BA1) A11 112
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HB52RD328DC-F
Front side Pin No. 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 Signal name Pin No. DQ10 DQ11 VCC 113 115 Back side Signal name Pin No. VCC DQMB2 DQMB3 VSS DQ24 DQ25 DQ26 DQ27 VCC 42 44 46 48 50 52 54 56 58 60 62 64 66 68 Signal name Pin No. DQ42 DQ43 VCC DQ44 DQ45 DQ46 DQ47 VSS NC NC CKE0 VCC CE CKE1 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 Signal name VCC DQMB6 DQMB7 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS SCL VCC
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117 DQ12 DQ13 DQ14 DQ15 VSS 119 121 123 125 127 NC NC CK0 VCC RE W S0 S1 129 131 133 135 137 139 141 143 4
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DQ28 DQ29 DQ30 DQ31 VSS SDA VCC
Data Sheet E0111H10
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70 NC 72 NC
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HB52RD328DC-F
Pin Description
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Pin name A0 to A11 A12/A13 S0/S1 RE CE W DQMB0 to DQMB7 CK0/CK1 CKE0/CKE1 SDA SCL VCC VSS NC DQ0 to DQ63
Function Address input Row address Column address Bank select address Data-input/output Chip select Row address asserted bank enable Column address asserted Write enable A0 to A11 A0 to A9 BA1, BA0
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Byte input/output mask Clock input Clock enable Data-input/output for serial PD Clock input for serial PD
Data Sheet E0111H10 5
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Power supply Ground No connection
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HB52RD328DC-F
Serial PD Matrix*1
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Byte No. Function described 0 1 2 3 4 5 6 7 8 9 Number of bytes used by module manufacturer Total SPD memory size Memory type Number of banks Module data width SDRAM cycle time (highest CE latency) 10 ns 10 11 12 Module configuration type Refresh rate/type 13 14 15 SDRAM width 16 17 SDRAM device attributes: Burst lengths supported 18 19 SDRAM device attributes: CE latency SDRAM device attributes: S latency 6
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 80 08 04 0C 0A 02 40 00 01 A0 128 256 byte SDRAM 12 10 2 64 0 (+) LVTTL CL = 3 *7 CL = 3 *7 Non parity Normal (15.625 s) Self refresh 16M x 4
Number of row addresses bits 0 Number of column addresses bits 0 0 0
Module data width (continued) 0 Module interface signal levels 0 1
SDRAM access from Clock (highest CE latency) 6 ns
Error checking SDRAM width
0 SDRAM device attributes: minimum clock delay for backto-back random column addresses 1 0
SDRAM device attributes: number of banks on SDRAM device
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0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Data Sheet E0111H10
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1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 1 0
0
0
60
0 0
0 0
00 80
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0 0 0 0 04 00 -- 0 1 01 1 CLK 1 0 1 0 8F 04 1, 2, 4, 8, full page 4 1 0 0 1 06 01 2, 3 0
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HB52RD328DC-F
Byte No. Function described 20 SDRAM device attributes: W latency Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 01 00 0E A0 0 Non buffer VCC 10% CL = 2 *7
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21 22 23 SDRAM device attributes: General SDRAM cycle time (2nd highest CE latency) (-A6F/A6FL) 10 ns (-B6F/B6FL) 15 ns 24 (-B6F/B6FL) 8 ns 25 SDRAM cycle time (3rd highest CE latency) Undefined 26 27 28 29 30 31 32 33 34 35 RE to CE delay min Minimum RE pulse width Density of each bank on module 36 to 61 Superset information 62 63 SPD data revision code (-B6F/B6FL) 64
SDRAM module attributes
1 0
1 1
1 1
1 0
0 0
0 0
0 0
0 0
F0 60 CL = 2 *7
SDRAM access from Clock (2nd highest CE latency) (-A6F/A6FL) 6 ns
SDRAM access from Clock (3rd 0 highest CE latency) Undefined Minimum row precharge time Row active to row active min
Address and command signal 0 input setup time Address and command signal 0 input hold time Data signal input setup time Data signal input hold time 0 0 0 0 0 1
Checksum for bytes 0 to 62 (-A6F/A6FL)
Manuf act urer's J EDEC I D c ode 0
65 to 71 Manuf act urer's J EDEC I D c ode 0
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1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0
0 0
0 0
0 0
0 0
0 0
80 00
0
0
0
0
0
0
00
Data Sheet E0111H10 7
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0 0 1 1 0 0 1 1 0 1 0 1 1 1 1 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0
0 0
0 0 0 0 0 0 0
14 14 14 32 20 20 10
20 ns 20 ns 20 ns 50 ns 2 bank 128M byte 2 ns*7 1 ns*7 2 ns*7 1 ns*7
0 1 0 0 0
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0 0 0 1 0 0 0 0 20 10 00 12 Future use Rev. 1.2A 1 1 13 19 1 1 83 131 1 0 1 0 07 00 HITACHI
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HB52RD328DC-F
Byte No. Function described 72 73 74 75 76 77 78 79 80 81 82 83 84 85 Manufacturing location Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments x 0 0 0 0 0 0 0 0 0 0 0 0 0 x 1 1 0 0 1 1 0 0 0 1 1 0 1 x 0 0 1 1 0 0 1 1 1 0 0 1 0 x 0 0 1 1 1 0 1 1 1 0 0 0 0 x 1 0 0 0 0 0 0 0 1 0 0 1 0 x 0 0 1 0 0 1 0 0 0 1 0 1 0 x 0 1 0 1 1 0 1 1 0 0 1 0 0 1 1 1 x 0 0 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 xx 48 42 35 32 52 44 33 32 38 44 43 2D 41 42 36 46 4C 20 * 3 (ASCII-8bit code) H B 5 2 R D 3 2 8 D C -- A B 6 F L (Space)
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(-B6D/B6DL) 86 87 88 89 90 91 92 93 94 Revision code Revision code Manufacturing date Manufacturing date 95 to 98 Assembly serial number 126 127 (-B6FD/B6FDL) 8
Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number (-A6D/A6DL)
Manufacturer's part number Manufacturer's part number Manufacturer's part number (L-version) Manufacturer's part number Manufacturer's part number Manufacturer's part number
99 t o 125 Manufacturer specific data Intel specification frequency
Intel specification CE# latency 1 support (-A6FD/A6FDL) 1
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0 1 0 0 0 1 0 1 0 0 0 0 0 x x *6 -- 0 -- 1 1 0 0 0 0 0 x x 1
Data Sheet E0111H10
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0 0 0 0 1 0 1 0 0 0 1 1 0 0 1 1 1 1 1 1 1 x x 0 0 0 0 0 1 0 x x 0 0 0 0 x x 0 0 0 0 x x -- 1 0 -- 0 -- 0 -- 1 0 0 1 0 0 0 1
0 0
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0 0 0 0 x x 0 0 0 0 x x 20 20 30 20 xx xx (Space) (Space) Initial (Space) Year code (BCD)*4 Week code (BCD)*4 -- 0 -- 0 -- *5 64 100 MHz 1 1 C7 CL = 2, 3 0 1 C5 CL = 3
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HB52RD328DC-F
Notes: 1. All serial PD data are not protected. 0: Serial data, "driven Low", 1: Serial data, "driven High" These SPD are based on Intel specification (Rev.1.2A) 2. Regarding byte32 to 35, based on JEDEC Committee Ballot JC42.5-97-119. 3. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows "J" on ASCII code.) 4. Regarding byte93 and 94, based on JEDEC Committee Ballot JC42.5-97-135. BCD is "Binary Coded Decimal". 5. All bits of 99 through 125 are not defined ("1" or "0"). 6. Bytes 95 through 98 are assembly serial number. 7. These specifications are defined based on component specification, not module.
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Data Sheet E0111H10 9
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HB52RD328DC-F
Block Diagram
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S0 S1 DQMB0 N0, N1 DQ0 to DQ7 DQMB1 N2, N3 DQ8 to DQ15 DQMB2 N4, N5 DQ16 to DQ23 DQMB3 N6, N7 DQ24 to DQ31 RE CE A0 to A11 BA0 BA1 CKE0 CKE1 WE CK0 CK1 VCC C0 to C15 VSS
CS DQMB
D0
CS D16 DQMB I/O0 to I/O3 CS D17 DQMB I/O0 to I/O3 CS D18 DQMB I/O0 to I/O3
DQMB4 N8, N9 DQ32 to DQ39
CS DQMB
D8
CS D24 DQMB I/O0 to I/O3 CS D25 DQMB I/O0 to I/O3 CS D26 DQMB I/O0 to I/O3 CS D27 DQMB I/O0 to I/O3 CS D28 DQMB I/O0 to I/O3 CS D29 DQMB I/O0 to I/O3 CS D30 DQMB I/O0 to I/O3 CS D31 DQMB I/O0 to I/O3
I/O0 to I/O3
I/O0 to I/O3 CS DQMB
CS DQMB
D1
D9
I/O0 to I/O3
I/O0 to I/O3 CS DQMB N10, N11 DQ40 to DQ47
CS DQMB
D2
DQMB5
D10
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I/O0 to I/O3 CS DQMB
I/O0 to I/O3 CS DQMB
D3
CS D19 DQMB I/O0 to I/O3
D11
I/O0 to I/O3
I/O0 to I/O3 CS DQMB N12, N13
CS DQMB
D4
CS D20 DQMB I/O0 to I/O3
DQMB6 DQ48 to DQ55
D12
I/O0 to I/O3 CS DQMB
I/O0 to I/O3 CS DQMB
I/O0 to I/O3 CS DQMB
I/O0 to I/O3 CS DQMB
I/O0 to I/O3
RAS (D0 to D31) CAS (D0 to D31) A0 to A11 (D0 to D31) BA0 (D0 to D31) BA1 (D0 to D31) CKE (D0 to D15) CKE (D16 to D31) WE (D0 to 31)
CLK (D0 to D3, D16 to D19) CLK (D4 to D7, D20 to D23) CLK (D8 to D11, D24 to D27) CLK (D12 to D15, D28 to D31) VCC (D0 to D31) VSS (D0 to D31)
Data Sheet E0111H10 10
Pr
D5
CS D21 DQMB I/O0 to I/O3
D13
I/O0 to I/O3 CS DQMB
D6
CS D22 DQMB I/O0 to I/O3
DQMB7
D14
N14, N15
DQ56 to DQ63
I/O0 to I/O3 CS DQMB
D7
CS D23 DQMB I/O0 to I/O3
D15
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I/O0 to I/O3 Serial PD SCL SCL A0 A1 A2 SDA SDA
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Notes: 1.SDA pull-up resister is required due to the open-drain/open-collector output. 2.SCL pull-up resistore is recommended because of the normal SCL line inactive "High" state. D0 to D3: HM5264405F U0: 2-kbit EEPROM C0 to C15: 0.1 F N0 to N15: Network resistors(10 )
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HB52RD328DC-F
Absolute Maximum Ratings
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Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Note: 1. Respect to VSS . Parameter Supply voltage VCC VSS Input high voltage Input low voltage Notes: 1. 2. 3. 4. 5. 6. VIH VIL
Symbol VT VCC Iout PT Topr Tstg
Value -0.5 to VCC + 0.5 ( 4.6 (max)) -0.5 to +4.6 50 4.0 0 to +65 -55 to +125
Unit V V mA W C C
Note 1 1
DC Operating Conditions (Ta = 0 to +65C)
Symbol Min 3.0 0 Max 3.6 0 Unit V V V V Notes 1, 2 3 1, 4, 5 1, 6
All voltage referred to VSS The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. CK, CKE, S, DQMB, DQ pins: VIH (max) = VCC + 0.5 V for pulse width 5 ns at VCC. Others: VIH (max) = 4.6 V for pulse width 5 ns at VCC. VIL (min) = -1.0 V for pulse width 5 ns at VSS .
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Data Sheet E0111H10 11
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2.0 -0.3 0.8
VCC + 0.3
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HB52RD328DC-F
VIL/VIH Clamp (Component characteristic)
I (mA)
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Minimum VIL Clamp Current
VIL (V) -2 -1.8 -1.6 -1.4 -1.2 -1 -0.9 -0.8 -0.6 -0.4 -0.2 0 0 -5 -10 -15 -20 -25 -30 -35 -2 12
This SDRAM component has VIL and VIH clamp for CK, CKE, S, DQMB and DQ pins.
I (mA) -32 -25 -19 -13 -8 -4 -2 -0.6 0
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-1.5
Data Sheet E0111H10
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0 0 0 -1 VIL (V)
-0.5
0
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HB52RD328DC-F
Minimum VIH Clamp Current
I (mA)
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VIH (V) VCC + 2 VCC + 1.8 VCC + 1.6 VCC + 1.4 VCC + 1.2 VCC + 1 VCC + 0.8 VCC + 0.6 VCC + 0.4 VCC + 0.2 VCC + 0 10 8 6 4 2 0 VCC + 0
I (mA) 10 8 5.5 3.5 1.5 0.3 0 0 0 0 0
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VCC + 0.5
Data Sheet E0111H10 13
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VCC + 1
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VCC + 1.5 VCC + 2 VIH (V)
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HB52RD328DC-F
IOL/IOH Characteristics (Component characteristic)
IOL (mA)
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Output Low Current (I OL)
Vout (V) 0 0.4 0.65 0.85 1 1.4 1.5 1.65 1.8 1.95 3 3.45 250 200 150 100 50 0 0 0.5 14
I OL
I OL Max (mA) 0 71 108 134 151 188 194 203 209 212 220 223
Min (mA) 0 27 41 51 58 70 72 75 77 77 80 81
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1 1.5 2 2.5 Vout (V) Data Sheet E0111H10
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min max 3 3.5
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HB52RD328DC-F
Output High Current (I OH ) (Ta = 0 to 65C, VCC = 3.0 V to 3.45 V, VSS = 0 V)
IOH (mA)
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Vout (V) 3.45 3.3 3 2.6 2.4 2 1.8 1.65 1.5 1.4 1 0 0 0 0.5 -100 -200 -300 -400 -500 -600
I OH
I OH Max (mA) -3 -28 -75 -130 -154 -197 -227 -248 -270 -285 -345 -503
Min (mA) -- --
0 -21 -34 -59
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-67 -73 -78 -81 -89 -93 1 1.5 2 2.5 Vout (V) Data Sheet E0111H10
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3
3.5
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min max
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HB52RD328DC-F
DC Characteristics (Ta = 0 to 65C, VCC = 3.3 V 0.3 V, VSS = 0 V)
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Parameter Operating current (CE latency = 2) (CE latency = 3) Standby current in power down Standby current in power down (input signal stable) Standby current in non power down Active standby current in power down Active standby current in non power down Burst operating current (CE latency = 2) (CE latency = 3) Refresh current Self refresh current Self refresh current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage I LI 16
HB52RD328DC -A6F/A6FL Max -B6F/B6FL Min Max Unit Test conditions Burst length = 1 t RC = min Notes 1, 2, 3
Symbol Min -- -- -- -- -- -- --
I CC1 I CC1 I CC2P
1248 -- 1248 -- 48 32 320 128 576 -- -- -- -- --
1248 mA 1248 mA 48 32 320 128 576 mA mA mA mA mA
CKE = VIL, t CK = 12 ns CKE = VIL, t CK = CKE, S = VIH, t CK = 12 ns CKE = VIL, t CK = 12 ns CKE, S = VIH, t CK = 12 ns t CK = min, BL = 4
6 7 4 1, 2, 6 1, 2, 4
I CC2PS I CC2N I CC3P
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I CC3N I CC4 I CC4 I CC5 I CC6 I CC6 -- -- -- -- -- -1 -1.5 2.4 -- I LO VOH VOL
Data Sheet E0111H10
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1168 -- 1168 -- 2048 -- 32 -- 1168 mA 1168 mA 2048 mA mA 32 12.8 1 1.5 -- 0.4 -- 12.8 1 mA A -1 -1.5 1.5 A 2.4 -- -- V 0.4 V
1, 2, 5
t RC = min VIH VCC - 0.2 V VIL 0.2 V 0 Vin VCC
2, 3 8
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0 Vout VCC DQ = disable I OH = -4 mA I OL = 4 mA
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HB52RD328DC-F
Notes: 1. I CC depends on output load condition when the device is selected. I CC (max) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CLK operating current. 7. After power down mode, no CLK operating current. 8. After self refresh mode set, self refresh current.
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Parameter Input capacitance (Address) Input capacitance (CK) Input capacitance (DQMB) Input/Output capacitance (DQ) Notes: 1. 2. 3. 4.
Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V)
Input capacitance (RE, CE, W, S, CKE)
Capacitance measured with Boonton Meter or effective capacitance measuring method. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing. DQMB = VIH to disable Dout. This parameter is sampled and not 100% tested.
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CIN CIN CIN CIN CI/O
Symbol
Max 150 150 90 30 30
Unit pF pF pF pF pF
Notes 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 3, 4
Data Sheet E0111H10 17
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HB52RD328DC-F
AC Characteristics (Ta = 0 to 65C, VCC = 3.3 V 0.3 V, VSS = 0 V)
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Parameter System clock cycle time (CE latency = 2) (CE latency = 3) t CK t CK CK high pulse width CK low pulse width t CKH t CKL Access time from CK (CE latency = 2) (CE latency = 3) Data-out hold time t AC t AC t OH CK to Data-out low impedance t LZ CK to Data-out high impedance t HZ Data-in setup time Data-in hold time Ref/Active to Ref/Active command period Active to Precharge command period Active command to column command (same bank) Precharge to active command period Write recovery or data-in to precharge lead time Active (a) to Active (b) command period Transition time (rise to fall) Refresh period t RC t RAS t RP t DPL tT t REF 18
HB52RD328DC -A6F/A6FL Max -- -- -- -- 6 6 -- -- 6 -B6F/B6FL Min 15 10 4 4 -- -- 3 2 -- Max -- -- -- -- 8 6 -- -- 6 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 1, 2 1, 2, 3 1, 4 1, 5, 6 1 1, 5 1 1 1 1, 2 Notes 1
PC100 Symbol Symbol Min Tclk Tclk Tch Tcl Tac Tac 10 10 4 4 -- -- 3 2 --
CKE setup time for power down t CESP exit
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Toh t AS , t CS, t DS, t CES Tsi Tpde Thi t AH, t CH, t DH, t CEH Trc Tras Trcd Trp Tdpl Trrd t RCD t RRD
Data Sheet E0111H10
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3 -- 3 3 -- 3 1 -- -- 1 70 50 20 20 10 20 1 -- 70 120000 -- -- -- 50 20 20 10 -- 5 20 1 64 --
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120000 ns 1 -- -- -- ns ns ns 1 1 1 -- 5 ns 1 ns 64 ms
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HB52RD328DC-F
Notes: 1. 2. 3. 4. 5. 6. AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V. Access time is measured at 1.5 V. Load condition is CL = 50 pF. t LZ (max) defines the time at which the outputs achieves the low impedance state. t HZ (max) defines the time at which the outputs achieves the high impedance state. t CES define CKE setup time to CK rising edge except power down exit command. t AS /tAH: Address, t CS/tCH: S, RE, CE, W, DQMB t DS/tDH: Data-in, t CES/tCEH : CKE
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Test Conditions
2.4 V 0.4 V
* Input and output timing reference levels: 1.5 V * Input waveform and output load: See following figures
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2.0 V 0.8 V t
T
input
I/O CL
Data Sheet E0111H10 19
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tT
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HB52RD328DC-F
Relationship Between Frequency and Minimum Latency
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Parameter Frequency (MHz) tCK (ns) Self refresh exit time Last data in to active command (Auto precharge, same bank) Self refresh exit to command input (CE latency = 3) Last data out to active command (auto precharge) (same bank) (CE latency = 3) Write command to data in latency DQMB to data in DQMB to data out CKE to CK disable Register set to active command 20
HB52RD328DC -A6F/A6FL/B6F/B6FL 100 Symbol lRCD lRC lRAS lRP lDPL lRRD Tdpl PC100 Symbol 10 2 7 5 2 1 2 Notes 1 = [lRAS+ lRP] 1 1 1 1 1 2 = [lDPL + lRP] = [lRC] 3
Active command to column command (same bank) Active command to active command (same bank) Active command to precharge command (same bank) Precharge command to active command (same bank) Write recovery or data-in to precharge command (same bank) Active command to active command (different bank)
Precharge command to high impedance (CE latency = 2)
Last data out to precharge (early precharge) (CE latency = 2)
Column command to column command
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Data Sheet E0111H10
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lSREX Tsrx 1 lAPW lSEC Tdal 3 7 lHZP lHZP lAPR Troh Troh 2 3 1 lEP lEP lCCD lWCD lDID lDOD lCLE lRSA -1 -2 1 Tccd Tdwd 0 0 2 Tdqm Tdqz Tcke 1 Tmrd 1
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HB52RD328DC-F
HB52RD328DC Parameter -A6F/A6FL/B6F/B6FL 100 Symbol lCDD lPEC lBSR lBSR lBSH lBSH lBSW PC100 Symbol 10 0 1 1 2 2 3 0 Notes
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Frequency (MHz) tCK (ns) S to command disable Power down exit to command input Burst stop to output valid data hold (CE latency = 2) (CE latency = 3) (CE latency = 3) Burst stop to write data ignore
Burst stop to output high impedance (CE latency = 2)
Notes: 1. lRCD to lRRD are recommended value. 2. Be valid [DSEL] or [NOP] at next command of self refresh exit. 3. Except [DSEL] and [NOP].
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Data Sheet E0111H10 21
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HB52RD328DC-F
Pin Functions
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22
CK0/CK1 (in pu t p in ): C K is the master cloc k input to this pin. The other input signals ar e re fe rre d at C K rising edge. S 0/S 1 (in pu t p in ): Whe n S is Low, the command input cyc le bec omes valid. Whe n S is High, all inputs ar e ignored. However, internal operations (bank active, burst operations, etc.) are held. RE, CE and W (input pins): Although these pin names are the same as those of conventional DRAM modules, they func tion in a diffe re nt wa y. The se pins def ine oper ation commands (r ea d, wr ite , etc .) depe nding on the combination of their voltage levels. For details, refer to the command operation section. A0 to A11 (in pu t p in s): R ow addr ess (A X0 to AX11) is dete rmined by A0 to A11 leve l at the bank ac tive command cycle CK rising edge. Column address (AY0 to AY7) is determined by A0 to A7 level at the read or wr ite command cyc le C K rising edge . And this column addr ess bec omes burst ac ce ss start addr ess. A10 def ines the pre cha rge mode. Whe n A10 = High at the pre cha rge command cyc le, both banks ar e pre cha rged. B ut whe n A10 = Low at the pre cha rge command cyc le, only the bank that is sele cted by A12/A13 (B A) is precharged. A12/A13 (input pin): A12/A13 is a bank select signal (BA). The memory array is divided into bank0, bank1, bank2 and bank3. If A12 is Low and A13 is Low, bank0 is selected. If A12 is High and A13 is Low, bank1 is selected. If A12 is Low and A13 is High, bank2 is selected. If A12 is High and A13 is HIgh, bank3 is selected. CKE0, CKE1 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next C K rising edge is valid. If C KE is Low, the next C K rising edge is invalid. This pin is used for powe r-dow n mode, clock suspend mode and self refresh mode. DQMB 0 to DQMB 7 (in pu t p in s): R ea d oper ation: If DQMB is High, the output buff er bec omes High-Z. If the DQMB is Low, the output buffer becomes Low-Z (The latency of DQMB during reading is 2 clocks). Wr ite oper ation: If DQMB is High, the pre vious data is held (the new data is not wr itten) . If DQMB is Low, the data is written (The latency of DQMB during writing is 0 clock). DQ0 to DQ63 (DQ pins): Data is input to and output from these pins. VCC (power supply pins): 3.3 V is applied. VSS (power supply pins): Ground is connected.
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Data Sheet E0111H10
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HB52RD328DC-F
Command Operation
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Command Truth Table
Command Ignore command No operation Burst stop in full page Read with auto-precharge Write with auto-precharge Precharge select bank Precharge all bank Refresh Mode register set
The SDRAM module recognizes the following commands specified by the S, RE, CE, W and address pins.
CKE Symbol DESL NOP BST n-1 n H H H H H H H H x x x x x x x x x x x S H L L L L L L L L L L L RE x H H H H H H L L L CE x H H L L L L H H H L W x H L H H L L H L L H L A0 A12/A13 A10 to A11 x x x V V V V V V x x V x x x L H L H V L H x V x x x V V V V V x x x V
Column address and read command READ
Column address and write command WRIT
Row address strobe and bank active ACTV PRE
Note: H: VIH. L: VIL. x: VIH or VIL. V: Valid address input
Ignore command [DESL]: When this command is set (S is High), the SDRAM module ignore command input at the clock. However, the internal status is held.
No op erat ion [N OP] : This command is not an exe cution command. Howe ver , the interna l oper ations continue.
Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page) and is illegal otherwise. When data input/output is completed for a full page of data, it automatically returns to the start address, and input/output is performed repeatedly. Column address strobe and read command [READ]: This command starts a read operation. In addition, the start address of burst read is determined by the column address and the bank select address (BA). After the read operation, the output buffer becomes High-Z.
Re ad with au to-p re ch arge [R EAD A] : This command automatica lly per forms a pre cha rge oper ation af ter a burst read with a burst length of 1, 2, 4 or 8. When the burst length is full-page, this command is illegal.
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READ A WRIT A PALL MRS
Data Sheet E0111H10 23
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H H REF/SELF H H V L L L
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HB52RD328DC-F
Colu mn ad dr ess str obe an d wr it e com man d [WR IT ]: This command starts a wr ite oper ation. Whe n the burst wr ite mode is sele cted, the column addr ess and the bank sele ct addr ess (B A) bec ome the burst wr ite start addr ess. Whe n the single wr ite mode is sele cted, data is only wr itten to the loca tion spec ified by the column address and the bank select address (BA). Writ e with au to-p re ch arge [WR IT A] : This command automatica lly per forms a pre cha rge oper ation af ter a burst write with a length of 1, 2, 4 or 8, or after a single write operation. When the burst length is full-page, this command is illegal. Row ad dr ess str obe an d b ank act ivate [A CTV ]: This command ac tiva tes the bank that is sele cted by bank sele ct addr ess (B A) and dete rmines the row addr ess (A X0 to AX11) . Whe n A12 and A13 ar e Low, bank 0 is activated. When A12 is High and A13 is Low, bank 1 is activated. When A12 is Low and A13 is High, bank 2 is activated. When A12 and A13 are High, bank 3 is activated. Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by A12/A13. If A12 and A13 are Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If A12 is Low and A13 is High, bank 2 is selected. If A12 and A13 are High, bank 3 is selected. Precharge all banks [PALL]: This command starts a precharge operation for all banks. Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation, the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section. Mod e re gister set [M RS ]: The S DRA M module has a mode re giste r that def ines how it oper ates. The mode register is specified by the address pins (A0 to A13) at the mode register set cycle. For details, refer to the mode re giste r conf iguration. Af te r powe r on, the conte nts of the mode re giste r ar e undef ined, exe cute the mode register set command to set up the mode register.
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Data Sheet E0111H10
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HB52RD328DC-F
DQMB Truth Table
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Command Write enable/output enable Write inhibit/output disable Note: H: VIH. L: VIL. x: VIH or VIL. Write: I DID is needed. Read: I DOD is needed.
CKE Symbol ENB MASK n-1 H H n x x DQMB L H
The SDRAM module can mask input/output data by means of DQMB. During reading, the output buffer is set to Low-Z by setting DQMB to Low, enabling data output. On the other hand, when DQMB is set to High, the output buffer becomes High-Z, disabling data output. During writing, data is written by setting DQMB to Low. When DQMB is set to High, the previous data is held (the new data is not wr itten) . De sir ed data ca n be maske d during burst re ad or burst wr ite by setting DQMB . For details, refer to the DQMB control section of the SDRAM module operating instructions.
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Pr
CKE n-1 n S H L x x x L L H H H H L H H L L L L L L H L L H L H H L L L H H H
CKE Truth Table
Current state Active Any Clock suspend Idle Idle Idle
Command
RE
CE x x x
W x x x
Address x x x
Clock suspend mode entry Clock suspend Clock suspend mode exit
x x x
uc od
L L H x x x x L L H x H x x x H x x x H x x x x x x H H H H H H
Auto-refresh command (REF) Self-refresh entry (SELF) Power down entry
Self refresh
Self refresh exit (SELFX)
Power down
Power down exit
Note: H: VIH. L: VIL. x: VIH or VIL.
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Data Sheet E0111H10 25
HB52RD328DC-F
Clock susp en d mod e en tr y: The S DRA M module ente rs cloc k suspend mode fr om ac tive mode by setting C KE to Low. If command is input in the cloc k suspend mode entr y cyc le, the command is valid. The cloc k suspend mode changes depending on the current status (1 clock before) as shown below. ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining the bank active status. RE AD susp en d an d RE AD with Au to-p re ch arge susp en d: The data being output is held (a nd continues to be output). WRITE suspend and WRIT with Auto-precharge suspend: In this mode, external signals are not accepted. However, the internal state is held. Clock suspend: During clock suspend mode, keep the CKE to Low. Clock susp en d mod e exit : The S DRA M module exits fr om cloc k suspend mode by setting C KE to High during the clock suspend state. IDLE: In this state, all banks are not selected, and completed precharge operation. Auto-refresh command [REF]: When this command is input from the IDLE state, the SDRAM module starts auto-refresh operation. (The auto-refresh is the same as the CBR refresh of conventional DRAMs.) During the auto- ref resh oper ation, re fre sh addr ess and bank sele ct addr ess ar e gene ra te d inside the S DRA M module. F or eve ry auto- ref resh cyc le, the interna l addr ess counte r is update d. Ac cordingly, 4096 time s ar e re quired to refresh the entire memory. Before executing the auto-refresh command, all the banks must be in the IDLE state. In addition, since the pre cha rge for all banks is automatica lly per forme d af ter auto- ref resh, no pre cha rge command is required after auto-refresh. S elf-r ef re sh en tr y [S E LF] : Whe n this command is input during the ID LE state, the S DRA M module starts self- re fre sh oper ation. Af te r the exe cution of this command, self- re fre sh continues while C KE is Low. S inc e self-refresh is performed internally and automatically, external refresh operations are unnecessary. Power down mode entry: When this command is executed during the IDLE state, the SDRAM module enters powe r down mode. In powe r down mode, powe r consumption is suppre sse d by cutting off the initia l input circuit. S elf-r ef re sh exit : Whe n this command is exe cute d during self- re fre sh mode, the S DRA M module ca n exit from self-refresh mode. After exiting from self-refresh mode, the SDRAM module enters the IDLE state. Powe r d own exit : Whe n this command is exe cute d at the powe r down mode, the S DRA M module ca n exit from power down mode. After exiting from power down mode, the SDRAM module enters the IDLE state.
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Data Sheet E0111H10
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HB52RD328DC-F
Function Truth Table
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Current state Precharge S RE x H x L L L L L L L L Idle H L L L L L L L L Row active H L L L L L L L L H H H H H H L L L L H H L x H H L L H H L L x H H L L H H L L L x H H H H L L L L x H H H H L L L L L L
The following table shows the operations that are performed when each command is issued in each mode of the SDRAM module. The following table assumes that CKE is high.
CE W x H L H L H L Address x x x Command DESL NOP BST Operation Enter IDLE after t RP Enter IDLE after t RP NOP ILLEGAL*4 ILLEGAL*4 ILLEGAL*4 NOP*6 ILLEGAL ILLEGAL NOP NOP NOP ILLEGAL*5 ILLEGAL*5 Bank and row active NOP Refresh
BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A BA, RA BA, A10 x ACTV PRE, PALL REF, SELF MRS DESL NOP BST
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H x H L L H L H L H L x H L H L H L H L
MODE x x x
Data Sheet E0111H10 27
Pr
BA, RA x MODE x x x ACTV BA, A10 PRE, PALL REF, SELF MRS DESL NOP BST BA, RA ACTV BA, A10 x MODE PRE, PALL REF, SELF MRS
BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A
BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A
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Mode register set NOP NOP NOP Begin read Begin write Other bank active ILLEGAL on same bank*3 Precharge ILLEGAL ILLEGAL
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HB52RD328DC-F
Current state Read S H RE x CE x W x H L H L H L H x Address x x x Command DESL NOP BST Operation Continue burst to end Continue burst to end Burst stop to full page Continue burst read to CE latency and New read Term burst read/start write Other bank active ILLEGAL on same bank*3 Term burst read and Precharge ILLEGAL ILLEGAL Continue burst to end and precharge Continue burst to end and precharge ILLEGAL ILLEGAL*4 ILLEGAL*4 Other bank active ILLEGAL on same bank*3 ILLEGAL*4 ILLEGAL
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L L L L L L L L Read with autoprecharge H L L L L L L L L Write H L L L L L L L L H H H H H H L L L L H H L x L x L L H H H H L L L L x H H H H L L L L H H L L H H L L x H H L L H H L L 28
BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A BA, RA BA, A10 x ACTV PRE, PALL REF, SELF MRS DESL NOP BST
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L H L H L H L H L x H L H L H L H L
MODE x x x
Data Sheet E0111H10
Pr
BA, RA ACTV BA, A10 x PRE, PALL REF, SELF MODE x x x MRS DESL NOP BST BA, RA ACTV BA, A10 x MODE PRE, PALL REF, SELF MRS
BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A
BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A
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ILLEGAL Continue burst to end Continue burst to end Burst stop on full page Term burst and New read Term burst and New write Other bank active ILLEGAL on same bank*3 Term burst write and Precharge*2 ILLEGAL ILLEGAL
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HB52RD328DC-F
Current state Write with autoprecharge S H RE x CE x W x H L H L H L H x Address x x x Command DESL NOP BST Operation Continue burst to end and precharge Continue burst to end and precharge ILLEGAL ILLEGAL*4 ILLEGAL*4 Other bank active ILLEGAL on same bank*3 ILLEGAL*4 ILLEGAL ILLEGAL Enter IDLE after t RC Enter IDLE after t RC Enter IDLE after t RC ILLEGAL*5 ILLEGAL*5 ILLEGAL*5 ILLEGAL*5 ILLEGAL ILLEGAL
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L L L L L L L L Refresh (autorefresh) H L L L L L L L L H H H H H H L L L L H H L x L x L L H H H H L L L L H H L L H H L L
BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A BA, RA BA, A10 x ACTV PRE, PALL REF, SELF MRS DESL NOP BST
Notes: 1. H: VIH. L: VIL. x: VIH or VIL. The other combinations are inhibit. 2. An interval of t DPL is required between the final valid data input and the precharge command. 3. If t RRD is not satisfied, this operation is illegal. 4. Illegal for same bank, except for another bank. 5. Illegal for all banks. 6. NOP for same bank, except for another bank.
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L H L H L H L H L
MODE x x x
Data Sheet E0111H10 29
Pr
BA, RA x ACTV BA, A10 PRE, PALL REF, SELF MODE MRS
BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A
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HB52RD328DC-F
From PRECHARGE state, command operation
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30
To [DESL], [NOP] or [BST]: When these commands are executed, the SDRAM module enters the IDLE state after tRP has elapsed from the completion of precharge.
From IDLE state, command operation To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation.
To [ACTV]: The bank specified by the address pins and the ROW address is activated. To [REF], [SELF]: The SDRAM module enters refresh mode (auto-refresh or self-refresh). To [MRS]: The SDRAM module enters the mode register set cycle.
From ROW ACTIVE state, command operation To [DESL], [NOP] or [BST]: These commands result in no operation.
To [READ], [READ A]: A read operation starts. (However, an interval of tRCD is required.) To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.) T o [A CTV ]: This command make s the other bank ac tive . (H oweve r, an interva l of tRRD is re quired. ) Attempting to make the currently active bank active results in an illegal command. T o [PR E] , [PA LL ]: The se commands set the S DRA M module to pre cha rge mode. (H oweve r, an interva l of tRAS is required.)
From READ state, command operation
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed. To [BST]: This command stops a full-page burst.
To [READ], [READ A]: Data output by the previous read command continues to be output. After CE latency, the data output resulting from the next command will start. To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle.
T o [A CTV ]: This command make s other banks bank ac tive . (H oweve r, an interva l of tRRD is re quired. ) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop a burst read, and the SDRAM module enters precharge mode.
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Data Sheet E0111H10
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HB52RD328DC-F
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From READ with AUTO-PRECHARGE state, command operation To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the SDRAM module then enters precharge mode. T o [A CTV ]: This command make s other banks bank ac tive . (H oweve r, an interva l of tRRD is re quired. ) Attempting to make the currently active bank active results in an illegal command.
From WRITE state, command operation To [DESL], [NOP]: These commands continue write operations until the burst operation is completed. To [BST]: This command stops a full-page burst. To [READ], [READ A]: These commands stop a burst and start a read cycle. To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle. T o [A CTV ]: This command make s the other bank ac tive . (H oweve r, an interva l of tRRD is re quired. ) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop burst write and the SDRAM module then enters precharge mode.
From WRITE with AUTO-PRECHARGE state, command operation
To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the SDRAM module enters precharge mode.
T o [A CTV ]: This command make s the other bank ac tive . (H oweve r, an interva l of tRRD is re quired. ) Attempting to make the currently active bank active results in an illegal command.
From REFRESH state, command operation
T o [D ES L] , [N OP] , [B S T] : Af te r an auto- ref resh cyc le (a fter tRC), the S DRA M module automatica lly ente rs the IDLE state.
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Data Sheet E0111H10 31
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HB52RD328DC-F
Simplified State Diagram
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Write WRITE SUSPEND CKE WRITEA SUSPEND CKE POWER APPLIED
SELF REFRESH SR ENTRY SR EXIT
MODE REGISTER SET
MRS IDLE
REFRESH
*1 AUTO REFRESH
Automatic transition after completion of command. Transition resulting from command input.
Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state.
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BST (on full page)
CKE CKE_ IDLE POWER DOWN
ACTIVE CLOCK SUSPEND
ACTIVE
CKE_
Pr
CKE ROW ACTIVE WRITE READ WRITE WRITE WITH AP READ READ WITH AP WRITE READ READ WITH AP WRITE WITH AP PRECHARGE WRITEA READA PRECHARGE PRECHARGE PRECHARGE PRECHARGE
BST (on full page)
Read CKE_ CKE READ SUSPEND
CKE_
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READ WITH AP CKE_ CKE READA SUSPEND
WRITE WITH AP CKE_
POWER ON
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Data Sheet E0111H10 32
HB52RD328DC-F
Mode Register Configuration
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A13 A12 A11 A10 A9 OPCODE 0 0 0 0 1 0 0 1 1 X A13 A12 A11 A10 0 X X X 0 X X X 0 X X X 0 X X X A9 0 0 1 1 A8 0 1 0 1 Note: only -A6.
The mode register is set by the input to the address pins (A0 to A13) during mode register set cycles. The mode register consists of five sections, each of which is assigned to address pins. A13, A12, A11, A10, A9 A8: (OPCODE ): The S DRA M module has two types of wr ite modes. One is the burst write mode, and the other is the single write mode. These bits specify write mode. B ur st re ad an d b ur st wr it e: B urst wr ite is per forme d for the spec ified burst length starting fr om the column address specified in the write cycle. B ur st re ad an d single wr it e: Da ta is only wr itten to the column addr ess spec ified during the wr ite cyc le, regardless of the burst length. A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set. A6, A5, A4: (LMODE): These pins specify the CE latency. A3: (BT): A burst type is specified. When full-page burst is performed, only "sequential" can be selected. A2, A1, A0: (BL): These pins specify the burst length.
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A8 A7 0 0 1 0 1 X R R
A6 A5 A4 CAS Latency R R 2* 3 R
Data Sheet E0111H10 33
Pr
A6 A5 A4 A3 LMODE BT A3 Burst Type 0 Sequential Interleave 1 Write mode Burst read and burst write Burst read and single write
A2
A1 BL
A0
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A2 A1 A0 0 0 0 0 1 1 1 0 0 1 1 0 1 0 1 0 1 0 0 Burst Length 1 2 4 1 2 4 8 BT=0 BT=1 8 R R R R R 1 0 1 R R 1 1 F.P. F.P. = Full Page R is Reserved (inhibit) X: 0 or 1
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HB52RD328DC-F
Burst Sequence
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Burst length = 2 A0 0 1 0, 1, 1, 0, Burst length = 8 Starting Ad. A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 34
Burst length = 4 Starting Ad. Addressing(decimal) A1 0 0 1 1 A0 0 1 0 1 Sequential 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, Interleave 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0,
Starting Ad. Addressing(decimal) Sequential Interleave 0, 1, 1, 0,
Addressing(decimal) Interleave 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 6, 2, 3, 0, 1, 6, 7, 4, 5, 3, 2, 1, 0, 7, 6, 5, 4, 4, 5, 6, 7, 0, 1, 2, 3, 5, 4, 7, 6, 1, 0, 3, 2, 6, 7, 4, 5, 2, 3, 0, 1, 7, 6, 5, 4, 3, 2, 1, 0, 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 0, 2, 3, 4, 5, 6, 7, 0, 1, 3, 4, 5, 6, 7, 0, 1, 2, 4, 5, 6, 7, 0, 1, 2, 3, 5, 6, 7, 0, 1, 2, 3, 4, 6, 7, 0, 1, 2, 3, 4, 5, 7, 0, 1, 2, 3, 4, 5, 6,
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A0 Sequential
Data Sheet E0111H10
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HB52RD328DC-F
Operation of the SDRAM module
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Read/Write Operations CE Latency
CK t RCD Command
ACTV
B ank act ive: B efor e exe cuting a re ad or wr ite oper ation, the cor re sponding bank and the row addr ess must be activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank 3 is activated according to the status of the bank sele ct addr ess (B A) pin, and the row addr ess (A X0 to AX11) is ac tiva ted by the A0 to A11 pins at the bank active command cycle. An interval of tRCD is required between the bank active command input and the following read/write command input. Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in the (CE Latency - 1) cycle after read command set. The SDRAM module can perform a burst read operation. The burst length can be set to 1, 2, 4, 8 or full-page. The start address for a burst read is specified by the column address and the bank select address (BA) at the read command set cycle. In a read operation, data output starts after the number of clocks specified by the CE Latency. The CE Latency can be set to 2 or 3. Whe n the burst length is 1, 2, 4 or 8, the Dout buff er automatica lly bec omes High-Z at the next cloc k af ter the successive burst-length data has been output. The CE latency and burst length must be specified at the mode register.
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READ Column
Pr uc od
out 1 out 2 out 3 out 0 out 1 out 2 out 3 CL = CE latency Burst Length = 4 out 0
Address
Row
Dout
CL = 2 CL = 3
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Data Sheet E0111H10 35
HB52RD328DC-F
Burst Length
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CK
t RCD
Command Address
ACTV
READ
Row
Column
BL = 1 BL = 2 BL = 4 BL = 8
out 0 out 0 out 1
Dout
out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7
out 0-1
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WRIT
Column
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 out 8
out 0
out 1
BL = full page
BL : Burst Length CE Latency = 2
Write operation: Burst write or single write mode is selected by the OPCODE (A13, A12, A11, A10, A9, A8) of the mode register. 1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the same clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set to 1, 2, 4, 8, and full-pa ge, like burst re ad oper ations. The wr ite start addr ess is spec ified by the column addr ess and the bank select address (BA) at the write command set cycle.
CK
Pr
in 2 in 2 in 2
t RCD
Command Address
ACTV
uc od
in 6 in 7 in 6 in 7 in 8
in 0-1
Row
BL = 1 BL = 2
in 0 in 0 in 1 in 1 in 1 in 1 in 3 in 3 in 3 in 4 in 4
Din
in 0
BL = 4
in 0
in 5
BL = 8
in 0
in 5
in 0
in 1
BL = full page
CE Latency = 2, 3
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Data Sheet E0111H10 36
HB52RD328DC-F
2. S in gle wr it e: A single wr ite oper ation is ena bled by setting OP CO DE (A 9, A8) to (1, 0). In a single wr ite oper ation, data is only wr itten to the column addr ess and the bank sele ct addr ess (B A) spec ified by the wr ite command set cycle without regard to the burst length setting. (The latency of data input is 0 clock).
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CK Command Address Din
t RCD
ACTV WRIT
Row
Column
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READ A lRAS READ A lRAS
in 0
Auto Precharge
Re ad with au to-p re ch arge : In this oper ation, since pre cha rge is automatica lly per forme d af ter completing a re ad oper ation, a pre cha rge command nee d not be exe cute d af ter ea ch re ad oper ation. The command exe cute d for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval defined by lAPR is required before execution of the next command.
Pr
out0 out1 out0
CE latency 3 2
Precharge start cycle
2 cycle before the final data is output 1 cycle before the final data is output
uc od
ACTV out2 out3 lAPR ACTV out1 out2 out3 lAPR
Burst Read (Burst Length = 4)
CK
CL=2 Command
ACTV
Dout
CL=3 Command
ACTV
Dout
Note: Internal auto-precharge starts at the timing indicated by " ". And an interval of tRAS (lRAS) is required between previous active (ACTV) command and internal precharge "
".
t
Data Sheet E0111H10 37
HB52RD328DC-F
Write with auto-precharge: In this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. The command exe cute d for the same bank af ter the exe cution of this command must be the bank ac tive (A CTV ) command. In addition, an interva l of lAP W is re quired betwe en the fina l valid data input and input of next command. Burst Write (Burst Length = 4)
EO
CK Command
ACTV
L
WRIT A
ACTV
IRAS in0 in1 in2 in3 lAPW
Din
Note: Internal auto-precharge starts at the timing indicated by " ". and an interval of tRAS (lRAS) is required between previous active (ACTV) command and internal precharge " ".
Pr
WRIT A
Single Write
uc od
ACTV
CK Command
ACTV
IRAS Din
in
lAPW
Note: Internal auto-precharge starts at the timing indicated by " ". and an interval of tRAS (lRAS) is required between previous active (ACTV) command and internal precharge " ".
t
Data Sheet E0111H10 38
HB52RD328DC-F
Full-page Burst Stop
EO
CE latency 2 3 1 2
CK Command Dout
out out
CK Command Dout out out
Burst stop command during burst read: The burst stop (BST) command is used to stop data output during a full-pa ge burst. The B ST command sets the output buff er to High-Z and stops the full-pa ge burst re ad. The timing from command input to the last data changes depending on the CE latency setting. In addition, the BST command is valid only during full-page burst mode, and is illegal with burst lengths 1, 2, 4 and 8.
BST to valid data BST to high impedance 2 3
CE Latency = 2, Burst Length = full page
CE Latency = 3, Burst Length = full page
L
Data Sheet E0111H10 39
Pr
BST out out out
BST out out out
out
l BSH = 2 cycle
l BSR = 1 cycle
uc od
out out l BSR = 2 cycle l BSH = 3 cycle
t
HB52RD328DC-F
B ur st stop com man d at b ur st wr it e: The burst stop command (B S T command) is used to stop data input during a full-pa ge burst wr ite . No data is wr itten in the same cloc k as the B ST command, and in subseque nt cloc ks. In addition, the B ST command is only valid during full-pa ge burst mode, and is ille gal with burst lengths of 1, 2, 4 and 8. And an interval of tDPL is required between last data-in and the next precharge command. Burst Length = full page
EO
CK Command Din in
BST in
PRE/PALL
L
t DPL
I BSW = 0 cycle
Data Sheet E0111H10 40
Pr uc od t
HB52RD328DC-F
Command Intervals
EO
CK Command
Address
BA
ACTV
READ
Read command to Read command interval: 1. Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 cloc k. Eve n whe n the first command is a burst re ad that is not yet finished, the data re ad by the second command will be valid. READ to READ Command Interval (same ROW address in same bank)
L
READ Column A Column B
Row
Pr
Bank0 Bank3 Dout Dout
Dout
Bank0 Active
out A0 out B0 out B1 out B2 out B3
Column =A Column =B Column =A Column =B Dout Read Read Dout
CE Latency = 3 Burst Length = 4 Bank 0
2. S ame b ank , d if fer en t ROW ad dr ess: Whe n the R OW addr ess cha nges on same bank, conse cutive re ad commands ca nnot be exe cute d; it is nec essa ry to sepa ra te the two re ad commands with a pre cha rge command and a bank-active command.
3. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1 cloc k, provide d that the other bank is in the bank- ac tive state. Eve n whe n the first command is a burst re ad that is not yet finished, the data read by the second command will be valid. READ to READ Command Interval (different bank)
CK Command
Address
BA
ACTV ACTV READ READ
uc od
CE Latency = 3 Burst Length = 4
Row 0
Row 1
Column A Column B
Dout
Bank0 Active Bank3 Bank0 Bank3 Active Read Read
out A0 out B0 out B1 out B2 out B3
t
41
Data Sheet E0111H10
HB52RD328DC-F
Write command to Write command interval:
EO
CK Command
Address
BA
ACTV WRIT
Row
1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the pre ce ding wr ite command, the sec ond wr ite ca n be per forme d af ter an interva l of no less than 1 clock. In the case of burst writes, the second write command has priority. WRITE to WRITE Command Interval (same ROW address in same bank)
WRIT
L
Column A Column B
Din
Bank0 Active
in A0
in B0
in B1
in B2
in B3
Column =A Column =B Write Write
Burst Write Mode Burst Length = 4 Bank 0
2. S ame b ank , d if fer en t ROW ad dr ess: Whe n the R OW addr ess cha nges, conse cutive wr ite commands ca nnot be exe cute d; it is nec essa ry to sepa ra te the two wr ite commands with a pre cha rge command and a bank-active command. 3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 cloc k, provide d that the other bank is in the bank- ac tive state. In the ca se of burst wr ite , the sec ond wr ite command has priority. WRITE to WRITE Command Interval (different bank)
Pr
WRIT in B0 in B1 in B2 in B3
uc od
Burst Write Mode Burst Length = 4
CK Command
Address
BA
ACTV ACTV WRIT
Row 0
Row 1
Column A Column B
Din
Bank0 Active
in A0
Bank3 Bank0 Bank3 Active Write Write
t
Data Sheet E0111H10 42
HB52RD328DC-F
Read command to Write command interval:
EO
CK Command
CL=2
DQMB
1. S ame b ank , same ROW ad dr ess: Whe n the wr ite command is exe cute d at the same R OW addr ess of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 clock. However, DQMB must be set High so that the output buffer becomes High-Z before data input. READ to WRITE Command Interval (1)
READ WRIT
L
in B0 High-Z
CL=3
Din
in B1
in B2
in B3
Dout
Burst Length = 4 Burst write
READ to WRITE Command Interval (2)
Pr
READ WRIT
CK Command
uc od
2 clock
DQMB
CL=2
High-Z
Dout
CL=3
High-Z
Din
2. S ame b ank , d if fer en t ROW ad dr ess: Whe n the R OW addr ess cha nges, conse cutive wr ite commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-active command.
3. Diff er en t b ank : Whe n the bank cha nges, the wr ite command ca n be per forme d af ter an interva l of no less than 1 clock, provided that the other bank is in the bank-active state. However, DQMB must be set High so that the output buffer becomes High-Z before data input.
t
Data Sheet E0111H10 43
HB52RD328DC-F
Write command to Read command interval:
EO
CK Command WRIT DQMB Din Dout in A0
CK Command DQMB Din Dout Column = A Write in A0 WRIT
1. S ame b ank , same ROW ad dr ess: Whe n the re ad command is exe cute d at the same R OW addr ess of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 cloc k. Howe ver , in the ca se of a burst wr ite , data will continue to be wr itten until one cyc le bef ore the re ad command is executed. WRITE to READ Command Interval (1)
READ
WRITE to READ Command Interval (2)
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be exe cute d; it is nec essa ry to sepa ra te the two commands with a pre cha rge command and a bank- ac tive command.
3. Diff er en t b ank : Whe n the bank cha nges, the re ad command ca n be per forme d af ter an interva l of no less than 1 clock, provided that the other bank is in the bank-active state. However, in the case of a burst write, data will continue to be written until one clock before the read command is executed (as in the case of the same bank and the same address).
L
out B0 Column = A Write Column = B Read out B1 out B2 out B3 Burst Write Mode CE Latency = 2 Burst Length = 4 Bank 0
in A1
Data Sheet E0111H10 44
Pr
CE Latency Column = B Dout
READ out B0 out B1 out B2 CE Latency Column = B Read Column = B Dout
uc od
out B3 Burst Write Mode CE Latency = 2 Burst Length = 4 Bank 0
t
HB52RD328DC-F
Read with auto precharge to Read command interval
EO
CK Command BA Dout READ A bank0 Read A CK Command BA Din in A0 bank0 Write A WRIT A
1. Diff er en t b ank : Whe n some banks ar e in the ac tive state, the sec ond re ad command (a nother bank) is exe cute d. Eve n whe n the first re ad with auto- prec har ge is a burst re ad that is not yet finished, the data re ad by the sec ond command is valid. The interna l auto- prec har ge of one bank starts at the next cloc k of the sec ond command. Read with Auto Precharge to Read Command Interval (Different bank)
READ
Note: Internal auto-precharge starts at the timing indicated by "
2. Same bank: The consecutive read command (the same bank) is illegal. Write with auto precharge to Write command interval
1. Diff er en t b ank : Whe n some banks ar e in the ac tive state, the sec ond wr ite command (a nother bank) is executed. In the case of burst writes, the second write command has priority. The internal auto-precharge of one bank starts at the next clock of the second command . Write with Auto Precharge to Write Command Interval (Different bank)
Note: Internal auto-precharge starts at the timing indicated by "
2. Same bank: The consecutive write command (the same bank) is illegal.
L
in A1
out A0
out A1
out B0
out B1 CE Latency = 3 Burst Length = 4
bank3 Read
Data Sheet E0111H10 45
Pr
". WRIT in B0 bank3 Write in B1 in B2 ".
uc od
in B3 Burst Length = 4
t
HB52RD328DC-F
Read with auto precharge to Write command interval
EO
CK Command BA DQMB CL = 2 CL = 3 Din Dout 46
Diff er en t b ank : Whe n some banks ar e in the ac tive state, the sec ond wr ite command (a nother bank) is executed. However, DQMB must be set High so that the output buffer becomes High-Z before data input. The internal auto-precharge of one bank starts at the next clock of the second command. Read with Auto Precharge to Write Command Interval (Different bank)
READ A
WRIT
Note: Internal auto-precharge starts at the timing indicated by "
2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It is necessary to separate the two commands with a bank active command.
L
in B0 bank0 Read A bank3 Write
in B1
in B2
in B3
High-Z
Data Sheet E0111H10
Pr
Burst Length = 4
".
uc od t
HB52RD328DC-F
Write with auto precharge to Read command interval
EO
CK Command BA WRIT A DQMB Din Dout bank0 Write A in A0
1. Diff er en t b ank : Whe n some banks ar e in the ac tive state, the sec ond re ad command (a nother bank) is exe cute d. Howe ver , in ca se of a burst wr ite , data will continue to be wr itten until one cloc k bef ore the re ad command is executed. The internal auto-precharge of one bank starts at the next clock of the second command. Write with Auto Precharge to Read Command Interval (Different bank)
READ
Note: Internal auto-precharge starts at the timing indicated by "
2. Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It is necessary to separate the two commands with a bank active command.
L
out B0 bank3 Read out B1 out B2 out B3 CE Latency = 3 Burst Length = 4 Data Sheet E0111H10 47
Pr
".
uc od t
HB52RD328DC-F
Read command to Precharge command interval (same bank):
EO
CK Command READ Dout
When the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one clock. However, since the output buffer then becomes High-Z after the cloc ks def ined by lHZ P, ther e is a ca se of interr uption to burst re ad data output will be interr upte d, if the precharge command is input during burst read. To read all data by burst read, the clocks defined by lEP must be assured as an interval from the final data output to precharge command execution. READ to PRECHARGE Command Interval (same bank): To output all data CE Latency = 2, Burst Length = 4
CE Latency = 3, Burst Length = 4
L
out A0 CL=2 out A1
PRE/PALL
out A2
out A3
l EP = -1 cycle
Pr
PRE/PALL
CK Command READ
uc od
out A1 out A2 out A3 l EP = -2 cycle
Dout CL=3
out A0
t
Data Sheet E0111H10 48
HB52RD328DC-F
READ to PRECHARGE Command Interval (same bank): To stop output data
EO
CK Command READ Dout
CE Latency = 2, Burst Length = 1, 2, 4, 8, full page burst
PRE/PALL High-Z
out A0 lHZP = 2
CE Latency = 3, Burst Length = 1, 2, 4, 8, full page burst
L
READ PRE/PALL
CK Command
Pr
out A0 High-Z lHZP = 3
Dout
Data Sheet E0111H10 49
uc od t
HB52RD328DC-F
Writ e com man d to Pr ech arge com man d int er val (sam e b ank ): Whe n the pre cha rge command is exe cute d for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 cloc k. Howe ver , if the burst wr ite oper ation is unfinished, the input data must be maske d by mea ns of DQMB for assurance of the clock defined by tDPL. WRITE to PRECHARGE Command Interval (same bank): Burst Length = 4 (To stop write operation)
EO
CK Command WRIT DQMB Din tDPL
PRE/PALL
L Pr
PRE/PALL
CK Command DQMB WRIT
Din
in A0
in A1
uc od
PRE/PALL
tDPL
Burst Length = 4 (To write all data)
CK Command DQMB WRIT
Din
in A0
in A1
in A2
in A3
tDPL
t
Data Sheet E0111H10 50
HB52RD328DC-F
Bank active command interval:
EO
CK Command ACTV Address ROW BA Bank 0 Active
1. Same bank: The interval between the two bank-active commands must be no less than tRC. Bank Active to Bank Active for Same Bank
ACTV
ROW
2. In the case of different bank-active commands: The interval between the two bank-active commands must be no less than tRRD. Bank Active to Bank Active for Different Bank
L
ACTV ROW:0 t RRD Bank 0 Active
t RC Bank 0 Active
Pr
ACTV ROW:1 Bank 3 Active
CK
uc od t
51
Command
Address
BA
Data Sheet E0111H10
HB52RD328DC-F
Mod e re gister set to B ank -ac tive com man d int er val: The interva l betwe en setting the mode re giste r and executing a bank-active command must be no less than lRSA .
EO
CK Command Address
MRS
ACTV
CODE
BS & ROW
L
Mode Register Set
I RSA Bank Active
DQMB Control The DQMB mask the DQ data. The timing of DQMB is different during reading and writing. Re adin g: Whe n data is re ad, the output buff er ca n be contr olle d by DQMB . B y setting DQMB to Low, the output buff er bec omes Low- Z, ena bling data output. B y setting DQMB to High, the output buff er bec omes High-Z, and the corresponding data is not output. However, internal reading operations continue. The latency of DQMB during reading is 2 clocks. Writ in g: Input data ca n be maske d by DQMB . B y setting DQMB to Low, data ca n be wr itten. In addition, when DQMB is set to High, the corresponding data is not written, and the previous data is held. The latency of DQMB during writing is 0 clock.
Data Sheet E0111H10 52
Pr
uc od t
HB52RD328DC-F
Reading
; ;;
DQMB Din in 0 in 1 in 3 l DID = 0 Latency Data Sheet E0111H10
EO
CK DQMB Dout
High-Z out 0 out 1 out 3
lDOD = 2 Latency
L
CK
Writing
Pr
uc od t
53
HB52RD328DC-F
Refresh
EO
Others
54
Au to-r ef re sh : All the banks must be pre cha rged bef ore exe cuting an auto- ref resh command. S inc e the autorefresh command updates the internal counter every time it is executed and determines the banks and the ROW addr esses to be re fre shed, exte rnal addr ess spec ifica tion is not re quired. The re fre sh cyc le is 4096 cyc les/64 ms. (4096 cyc les ar e re quired to re fre sh all the R OW addr esses. ) The output buff er bec omes High-Z af ter auto- ref resh start. In addition, since a pre cha rge has bee n complete d by an interna l oper ation af ter the autorefresh, an additional precharge operation by the precharge command is not required.
S elf-r ef re sh : Af te r exe cuting a self- re fre sh command, the self- re fre sh oper ation continues while C KE is held Low. Dur ing self- re fre sh oper ation, all R OW addr esses ar e re fre shed by the interna l re fre sh time r. A selfre fre sh is ter mina te d by a self- re fre sh exit command. B efor e and af ter self- re fre sh mode, exe cute auto- ref resh to all refresh addresses in or within 64 ms period on the condition (1) and (2) below. (1) Enter self-refresh mode within 15.6 s after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. (2) Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6 s after exiting from self-refresh mode.
Powe r- down mod e: The S DRA M module ente rs powe r-dow n mode whe n C KE goes Low in the ID LE state. In powe r down mode, powe r consumption is suppre sse d by dea ctivating the input initia l cir cuit. P ower down mode continues while C KE is held Low. In addition, by setting C KE to High, the S DRA M module exits fr om the power down mode, and command input is enabled from the next clock. In this mode, internal refresh is not performed. Clock susp en d mod e: B y driving C KE to Low during a bank- ac tive or re ad/wr ite oper ation, the S DRA M module ente rs cloc k suspend mode. Dur ing cloc k suspend mode, exte rnal input signals ar e ignore d and the interna l state is maintained. Whe n C KE is drive n High, the S DRA M module ter mina te s cloc k suspend mode, and command input is enabled from the next clock. For details, refer to the "CKE Truth Table". Power-up sequence: The SDRAM module should be gone on the following sequence with power up.
The CK, CKE, S, DQMB and DQ pins keep low till power stabilizes. The CK pin is stabilized within 100 s after power stabilizes before the following initialization sequence. The CKE and DQMB is driven to high between power stabilizes and the initialization sequence.
This SDRAM module has VCC clamp diodes for CK, CKE, S, DQMB and DQ pins. If these pins go high before power up, the large current flows from these pins to VCC through the diodes.
Initialization sequence: When 200 s or more has past after the above power-up sequence, all banks must be precharged using the precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF). S et the mode re giste r set command (MR S) to initia liz e the mode re giste r. We re commend that by kee ping DQMB to High, the output buff er bec omes High-Z during Initializa tion seque nce , to avoid DQ bus conte ntion on memory system formed with a number of device.
L
Data Sheet E0111H10
Pr
uc od t
HB52RD328DC-F
Power up sequence Initialization sequence 100 s 200 s
EO
VCC 0V CKE, DQMB CK Low Low Low S, DQ
Power stabilize
L
Data Sheet E0111H10 55
Pr uc od t
HB52RD328DC-F
Timing Waveforms
;; ;; ;;;
Read Cycle
t CK t CKH t CKL
;; ;; ;;;;; ; ;; ;;; ;;; ;; ;;
VIH
EO
CK CKE
t RCD t CS t CH
t RC
t RAS
t RP
t CS t CH
t CS t CH
t CS t CH
S
t CS t CH
L
t CS t CH t CS t CH t CS t CH t AS t AH t AS t AH t AS t AH t CS t AC Bank 0 Read t LZ
t CS t CH
t CS t CH
RE
t CS t CH
t CS t CH
t CS t CH
CE
t CS t CH
t CS t CH
t CS t CH
Pr
t AS t AH t AS t AH t CH t AC t AC t AC t OH t OH t OH t OH Bank 0 Precharge
W
t AS t AH t AS t AH
t AS t AH t AS t AH
A12/A13
A10
t AS t AH
t AS t AH
Address
uc od
t HZ
DQMB
Din
Dout
Bank 0 Active
CE latency = 2 Burst length = 4 Bank 0 access = VIH or VIL
t
Data Sheet E0111H10 56
HB52RD328DC-F
Write Cycle
;; ; ;; ;;;;
EO
t CK t CKH t CKL
CK
t RC
VIH
CKE
t RCD
t RAS
t RP
;; ; ; ;;
t CS t CH t CS t CH t CS t CH t CS t CH
S
t CS t CH
t CS t CH
t CS t CH
t CS t CH
RE
t CS t CH
L
t CS t CH t CS t CH t AS t AH t AS t AH t AS t AH t CS t DS t DH tDS Bank 0 Write
t CS t CH
t CS t CH
CE
t CS t CH
t CS t CH
t CS t CH
W
t AS t AH t AS t AH
t AS t AH
t AS t AH t AS t AH
A12/A13
Pr
t AS t AH t CH t DH t DS t DH t DS t DH t DPL
A10
t AS t AH
t AS t AH
Address
DQMB
uc od
Bank 0 Precharge
Din
Dout
Bank 0 Active
CE latency = 2 Burst length = 4 Bank 0 access = VIH or VIL
t
57
Data Sheet E0111H10
;;; ;; ;
HB52RD328DC-F
Mode Register Set Cycle
0 1
;; ; ;;; ;; ;; ;;;; ;; ;;;; ; ;;; ; ;;
EO
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
CK
CKE S
VIH
RE CE W
BA
L
code R: b l RP l RSA l RCD
Mode Bank 3 register Active Set
Address
valid
C: b
C: b'
DQMB Dout Din
b
b+3
b'
b'+1
b'+2
b'+3
High-Z
Output mask
Precharge If needed
Bank 3 Read
l RCD = 3 CE latency = 3 Burst length = 4 = VIH or VIL
Data Sheet E0111H10 58
Pr
uc od
t
;;;; ;; ;; ;
HB52RD328DC-F
Read Cycle/Write Cycle
0 1 2
;;;; ;; ;;; ;; ;
EO
3 4 CK S CKE RE CE W BA
VIH
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Read cycle RE-CE delay = 3 CE latency = 3 Burst length = 4 = VIH or VIL
Address DQMB Din
R:a
C:a
R:b
C:b
C:b'
C:b"
Dout
a
a+1 a+2 a+3
b
b+1 b+2 b+3 b'
Bank 3 Read
b'+1 b"
b"+1 b"+2 b"+3
High-Z
L
Bank 0 Read Bank 3 Active
Bank 0 Active
Bank 3 Bank 0 Read Precharge
Bank 3 Read
Bank 3 Precharge
CKE S RE CE W BA
VIH
Write cycle RE-CE delay = 3 CE latency = 3 Burst length = 4 = VIH or VIL
Pr
C:b C:b' C:b"
High-Z
Address DQMB Dout
R:a
C:a
R:b
Din
a
a+1 a+2 a+3
Bank 3 Active
b
b+1 b+2 b+3 b'
Bank 0 Precharge
b'+1 b"
b"+1 b"+2 b"+3
Bank 0 Active
Bank 0 Write
Bank 3 Write
Bank 3 Write
Bank 3 Write
Bank 3 Precharge
Data Sheet E0111H10 59
uc od
t
;;; ; ; ;; ; ;
HB52RD328DC-F
Read/Single Write Cycle
0 1
;;; ; ; ; ; ;
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CK CKE RE CE W BA
VIH
EO
S Address Din R:a C:a DQMB Dout
Bank 0 Active Bank 0 Read
R:b
C:a' C:a a
L
a
Bank 3 Active
a+1 a+2 a+3
a
a+1 a+2 a+3
Bank 0 Precharge
Bank 0 Bank 0 Write Read
Bank 3 Precharge
CKE
VIH
S
RE CE W BA
Pr
R:b C:a a b a a+1 a+3
Bank 3 Active Bank 0 Write
Address
R:a
C:a
C:b C:c c
DQMB Din Dout
Bank 0 Active
Bank 0 Read
Bank 0 Bank 0 Write Write
Bank 0 Precharge
Data Sheet E0111H10 60
uc od
Read/Single write RE-CE delay = 3 CE latency = 3 Burst length = 4 = VIH or VIL
t
;; ; ; ; ;;
HB52RD328DC-F
Read/Burst Write Cycle
0 1
; ;; ;
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CK S CKE RE CE W BA Address DQMB R:a C:a R:b C:a' a
EO
Din Dout
Bank 0 Active Bank 0 Read
L
a
Bank 3 Active
a+1 a+2 a+3
a+1 a+2 a+3
Clock suspend
Bank 0 Write
Bank 0 Precharge
Bank 3 Precharge
CKE S
VIH
RE CE W BA
Pr
R:b C:a a a a+1 a+3
Bank 3 Active Bank 0 Write
Address DQMB
R:a
C:a
Din
a+1 a+2 a+3
Dout
Bank 0 Active
Bank 0 Read
Bank 0 Precharge
Data Sheet E0111H10
uc od
Read/Burst write RE-CE delay = 3 CE latency = 3 Burst length = 4 = VIH or VIL
t
61
;;; ;; ;;
HB52RD328DC-F
Full Page Read/Write Cycle
CK
CKE
VIH
S
RE CE BA
W
Address
R:a
C:a
R:b
DQMB Dout
a
a+1
a+2
Din
Bank 0 Active
Bank 0 Read
Bank 3 Active
CKE
VIH
S
RE CE BA
W
Address
R:a
C:a
R:b
DQMB
Dout
Din
a
a+1
a+2
a+3
a+4
a+5
Bank 0 Active
Bank 0 Write
Bank 3 Active
; ; ;
Read cycle RE-CE delay = 3 CE latency = 3 Burst length = full page = VIH or VIL
a+3
EO
62
High-Z
Burst stop
Bank 3 Precharge
L
Write cycle RE-CE delay = 3 CE latency = 3 Burst length = full page = VIH or VIL
Data Sheet E0111H10
Pr
High-Z
a+6
Burst stop
Bank 3 Precharge
uc od
t
; ;;;; ;; ;;;;; ;;;
HB52RD328DC-F
Auto Refresh Cycle
0
;;;; ; ;; ;;; ;;; ;; ; ;;; ; ;; ;;;;;;;;; ;;;; ;;;; ; ;;; ; ;;; ;; ; ; ;; ; ;;
EO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
CK
CKE S
VIH
RE CE W
BA
Address DQMB Din
A10=1
R:a
C:a
L
t RP t RC
Auto Refresh
CKE Low Self refresh entry command
Dout
High-Z
a
a+1
tRC
Precharge If needed
Auto Refresh
Active Bank 0
Read Bank 0
Refresh cycle and Read cycle RE-CE delay = 2 CE latency = 2 Burst length = 4 = VIH or VIL
Pr
l SREX
Self Refresh Cycle
CK
CKE S
uc od
tRC tRC
Next clock enable Self refresh entry command Auto Next clock refresh enable
RE CE W
BA
Address DQMB Din
A10=1
Dout
High-Z
tRP
Precharge command If needed
Self refresh exit ignore command or No operation
Self refresh cycle RE-CE delay = 3 CE latency = 3 Burst length = 4 = VIH or VIL
t
63
Data Sheet E0111H10
;;;; ;;; ;;
HB52RD328DC-F
Clock Suspend Mode
t CES
t CEH
t CES
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CK S
CKE RE CE W BA
Address
R:a
C:a
R:b
C:b
DQMB
Dout Din
a
a+1 a+2
a+3
b
b+1 b+2 b+3
High-Z
Bank0 Active clock Active suspend start
Active clock Bank0 suspend end Read
Bank3 Active
Read suspend start
Read suspend end
Bank3 Read
Bank0 Precharge
CKE S
RE CE W BA
Address
R:a
C:a R:b
C:b
DQMB
Dout Din
High-Z
a
a+1 a+2
a+3 b
b+1 b+2 b+3
Bank0 Active
Active clock suspend start
Active clock Bank0 Bank3 supend end Write Active
Write suspend start
Write suspend end
Bank3 Bank0 Write Precharge
;
17 18 19 20
;; ;;;; ; ;;;; ; ; ;;; ;; ; ;;; ;;;;
Read cycle RE-CE delay = 2 CE latency = 2 Burst length = 4 = VIH or VIL
EO
64
L
Earliest Bank3 Precharge
Write cycle RE-CE delay = 2 CE latency = 2 Burst length = 4 = VIH or VIL
Data Sheet E0111H10
Pr
Earliest Bank3 Precharge
uc od
t
;; ;; ;; ; ; ;
HB52RD328DC-F
Power Down Mode
;; ;; ;;; ; ;;; ;; ;; ; ;; ;
0 1 2 3 4 5 6 7 8 9 10 48 49 50 51 52 53 54 55
;;; ; ;;; ;;; ;; ;; ;;; ; ; ;; ;; ; ;;
CKE S
CKE Low
EO
CK RE CE W BA Address DQMB Din
A10=1
L
tRP
t RP
Auto Refresh
R: a
Pr
High-Z
Power down entry
t RC tRC
Auto Refresh
Dout
Precharge command If needed
Power down mode exit Active Bank 0
Power down cycle RE-CE delay = 3 CE latency = 3 Burst length = 4 = VIH or VIL
uc od
code Valid High-Z t RSA
Mode register Set Bank active If needed
Initialization Sequence
CK
CKE
VIH
S
RE CE W
Address
valid
DQMB
VIH
DQ
All banks Precharge
t
65
Data Sheet E0111H10
HB52RD328DC-F
Physical Outline
31.75 1.250
3.30 0.130
23.20 0.913 2.50 0.098
B
4.60 0.181
32.80 1.291
A 1.00 0.10 0.039 0.004
Component area (back) 2-R2.00 2-R0.079
(Datum -A-)
2.00 Min 0.079 Min
Detail A
0.60 0.05 0.024 0.002 0.25 Max 0.010 Max 0.100 Min 2.55 Min
Detail B
4.00 0.10 0.157 0.004
3.70 0.146
2
2.10 0.083 23.20 0.913
4.60 0.181 32.80 1.291
144
143
1
3.20 Min 0.126 Min
20.00 0.787
Component area (front)
(DATUM -A-)
2.5 0.098
R0.75 R0.030
0.80 0.031
4.00 0.10 0.157 0.004
1.50 0.10 0.059 0.004
4.00 Min 0.157 Min
EO
66
67.60 2.661 (Datum -A-) 2R3.00 Min 2R0.118 Min
Unit: mm inch 3.80 Max 0.150 Max
L
Data Sheet E0111H10
Pr
uc od t
HB52RD328DC-F
Cautions
EO
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.'s or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products.
L
Data Sheet E0111H10 67
Pr
uc od t

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